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1 for more information www.linear.com/ltc3872 no r sense current mode boost dc/dc controller high efficiency 3.3v input, 5v output boost converter i th iprg gnd v fb v in sw ngate ltc3872 3872 ta01 run/ss 17.4k v in 11k 1% 34.8k 1% 1nf m1 d1 10f 100f 2 1.8nf 47pf 1h v in 3.3v v out 5v 2a efficiency and power loss vs load current load current (ma) 30 efficiency (%) power loss (w) 90 100 10 0.001 20 10 80 50 70 60 40 1 100 1000 10000 3872 ta01b 0 10 1 0.1 0.01 typical a pplica t ion fea t ures descrip t ion a pplica t ions the lt c ? 3872 is a constant frequency current mode boost dc/dc controller that drives an n-channel power mosfet and requires very few external components. the no r sense tm architecture eliminates the need for a sense resistor, improves efficiency and saves board space. the ltc3872 provides excellent ac and dc load and line regulation with 1.5% output voltage accuracy. it incor - porates an undervoltage lockout feature that shuts down the device when the input voltage falls below 2.3v. high switching frequency of 550khz allows the use of a small inductor. the l tc3872 is available in an 8-lead low profile (1mm) thinsot tm package and 8-pin 2mm 3mm dfn package. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n telecom power supplies n 42v automotive systems n 24v industrial controls n ip phone power supplies n no current sense resistor required n v out up to 60v n constant frequency 550khz operation n internal soft-start and optional external soft-start n adjustable current limit n pulse skipping at light load n v in range: 2.75v to 9.8v n 1.5% voltage reference accuracy n current mode operation for excellent line and load transient response n low profile (1mm) sot-23 and 2mm 3mm dfn packages ltc3872 3872fc
2 for more information www.linear.com/ltc3872 input supply voltage (v in ), run/ss .......... C0. 3v to 10v iprg voltage ................................. C0. 3v to (v in + 0.3v) v fb , i th voltages ....................................... C0. 3v to 2.4v sw voltage ................................................ C0. 3v to 60v operating junction temperature range (notes 2, 3) ............................................ C40 c to 150c storage temperature range .................. C65 c to 150c lead temperature (soldering, 10 sec) ts8 package ......................................................... 300c a bsolu t e maxi m u m r a t ings o r d er i n f or m a t ion iprg 1 i th 2 v fb 3 gnd 4 8 sw 7 run/ss 6 v in 5 ngate top view ts8 package 8-lead plastic tsot-23 t jmax = 150c, ja = 195c/w top view 9 ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1gnd v fb i th iprg ngate v in run/ss sw t jmax = 150c, ja = 76c/w exposed pad (pin 9) is gnd must be soldered to pcb p in c on f igura t ion lead free finish tape and reel part marking* package description temperature range ltc3872ets8#pbf ltc3872ets8#trpbf lcgb 8-lead plastic tsot-23 C40c to 85c ltc3872its8#pbf ltc3872its8#trpbf lcgb 8-lead plastic tsot-23 C40c to 125c ltc3872hts8#pbf ltc3872hts8#trpbf lcgb 8-lead plastic tsot-23 C40c to 150c ltc3872eddb#pbf ltc3872eddb#trpbf lcht 8-lead (3mm 2mm) plastic dfn C40c to 85c ltc3872iddb#pbf ltc3872iddb#trpbf lcht 8-lead (3mm 2mm) plastic dfn C40c to 125c ltc3872hddb#pbf ltc3872hddb#trpbf lcht 8-lead (3mm 2mm) plastic dfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear .com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ (note 1) ltc3872 3872fc
3 for more information www.linear.com/ltc3872 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3872 is tested under pulsed load conditions such that t j ??t a . the ltc3872e is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3872i is guaranteed over the C40c to 125c operating junction temperature range. the ltc3872h is guaranteed over the full C40c to 150c operating junction temperature range. the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. parameter conditions min typ max units input voltage range l 2.75 9.8 v input dc supply current normal operation shutdown uvlo typicals at v in = 4.2v (note 4) 2.75v v in 9.8v v run/ss = 0v v in < uvlo threshold 250 8 20 400 20 35 a a a undervoltage lockout threshold v in rising v in falling l l 2.3 2.05 2.45 2.3 2.75 2.55 v v shutdown threshold (at run/ss) v run/ss falling v run/ss rising l l 0.6 0.65 0.85 0.95 1.05 1.15 v v regulated feedback voltage (note 5) ltc3872e l tc3872i and l tc3872h l l 1.182 1.178 1.2 1.2 1.218 1.218 v v feedback voltage line regulation 2.75v < v in < 9v (note 5) 0.14 mv/v feedback voltage load regulation v ith = 1.6v (note 5) v ith = 1v (note 5) 0.05 C0.05 % % v fb input current (note 5) 25 50 na run/ss pull up current v run/ss = 0 0.35 0.7 1.25 a oscillator frequency normal operation v fb = 1v 500 550 650 khz gate drive rise time c load = 3000pf 40 ns gate drive fall time c load = 3000pf 40 ns peak current sense voltage iprg = gnd (note 6) ltc3872e ltc3872i ltc3872h l l l 80 70 65 100 100 100 120 120 120 mv mv mv iprg = float ltc3872e ltc3872i ltc3872h l l l 145 135 130 170 170 170 195 195 195 mv mv mv iprg = v in ltc3872e ltc3872i ltc3872h l l l 240 225 215 270 270 270 290 290 290 mv mv mv default internal soft-start time 1 ms the l denotes the specifications which apply over the specified operating temperature range, otherwise specifications are at t a = 25c (note 2). v in = 4.2v unless otherwise noted. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc3872ts8: t j = t a + (p d ? 195c/w) ltc3872ddb: t j = t a + (p d ? 76c/w) note 4: the dynamic input supply current is higher due to power mosfet gate charging (q g ? f osc ). see applications information. note 5: the ltc3872 is tested in a feedback loop which servos v fb to the reference voltage with the i th pin forced to the midpoint of its voltage range (0.7v v ith 1.9v, midpoint = 1.3v). note 6: rise and fall times are measured at 10% and 90% levels. e lec t rical c harac t eris t ics ltc3872 3872fc
4 for more information www.linear.com/ltc3872 duty cycle (%) 0 frequency (khz) 200 400 600 100 300 500 20 40 60 80 3278 g06 100 100 30 50 70 90 v in (v) 2 shutdown mode iq (a) 8 10 12 8 3872 g04 6 4 4 3 5 7 9 6 10 2 0 14 temperature (c) ?50 0 shutdown iq (a) 5 10 15 20 ?25 0 25 50 3872 g05 75 100 125 150 shutdown i q vs v in shutdown i q vs temperature frequency vs duty cycle typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. temperature (c) ?60 fb voltage (v) 1.22 1.23 1.24 6040 3872 g01 1.21 1.20 ?20?40 200 100 80 1.19 1.18 1.25 v in (v) 0 1.1990 fb voltage (v) 1.1995 1.2005 1.2010 1.2015 1.2025 1 5 7 3872 g02 1.2000 1.2020 4 9 10 2 3 6 8 run voltage (v) 0 i th voltage (v) 1.5 2.0 2.5 4.0 3872 g03 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5 5.0 v in = 2.5v v in = 3.3v v in = 5v fb voltage vs temperature fb voltage line regulation i th voltage vs run/ss voltage ltc3872 3872fc
5 for more information www.linear.com/ltc3872 c load (pf) 0 time (ns) 60 80 100 8000 3872 g07 40 20 50 70 90 30 10 0 2000 4000 6000 10000 rise time fall time v in (v) 0 run thresholds (v) 0.90 0.92 0.94 6 10 3872 g08 0.88 0.86 0.84 2 4 8 0.96 0.98 1.00 12 rising falling temperature (c) ?50 run thresholds (v) 0.8 0.9 1.0 25 75 150 3872 g09 0.7 0.6 0.5 ?25 0 50 100 125 rising falling temperature (c) ?50 500 frequency (khz) 525 550 575 600 ?5 0 25 50 3872 g10 75 100 125 150 temperature (c) 0 maximum sense threshold (mv) 100 200 300 50 150 250 ?10 30 70 110 3872 g11 150 ?30?50 10 50 90 130 iprg = v in iprg = float iprg = gnd gate drive rise and fall time vs c load run/ss threshold vs v in run/ss threshold vs temperature frequency vs temperature maximum sense threshold vs temperature typical p er f or m ance c harac t eris t ics t a = 25c, unless otherwise noted. ltc3872 3872fc
6 for more information www.linear.com/ltc3872 iprg (pin 1/pin 4): current sense limit select pin. i th (pin 2/pin 3): it serves as the error amplifier com - pensation point. nominal voltage range for this pin is 0.7v to 1.9v. v fb (pin 3/pin 2): receives the feedback voltage from an external resistor divider across the output. gnd (pin 4/pin 1, exposed pad pin 9): ground. the ex - posed pad must be soldered to pcb ground for electrical contact and rated thermal performance. ngate (pin 5/pin 8): gate drive for the external n-channel mosfet . this pin swings from 0v to v in . v in (pin 6/pin 7): supply pin. this pin must be closely decoupled to gnd. run/ss (pin 7/pin 6): shutdown and external soft-start pin. in shutdown, all functions are disabled and the ngate pin is held low. sw (pin 8/pin 5): switch node connection to inductor and current sense input pin through external slope compensa - tion resistor. normally, the external n-channel mosfets drain is connected to this pin. run/ss v in sw gnd i th v fb ngate 3872 fd iprg slope compensation 550khz oscillator current comparator sr q v in voltage reference undervoltage lockout ? + i th buffer switching logic circuit current limit clamp internal soft-start ramp ? + i lim rs latch 1.2v 1.2v uv shutdown comparator shdn error amplifier 0.7a ? + f unc t ional d iagra m p in func t ions (ts8/dd8) ltc3872 3872fc
7 for more information www.linear.com/ltc3872 main control loop the ltc3872 is a no r sense constant frequency, current mode controller for dc/dc boost, sepic and flyback converter applications. the ltc3872 is distinguished from conventional current mode controllers because the current control loop can be closed by sensing the voltage drop across the power mosfet switch or across a discrete sense resistor, as shown in figures 1 and 2. this no?r sense sensing technique improves efficiency, increases power density and reduces the cost of the overall solution. for circuit operation, please refer to the block diagram of the ic and the typical application on the front page. in normal operation, the power mosfet is turned on when the oscillator sets the rs latch and is turned off when the current comparator resets the latch. the divided-down output voltage is compared to an internal 1.2v reference by the error amplifier, which outputs an error signal at the i th pin. the voltage on the i th pin sets the current comparator input threshold. when the load current increases, a fall in the fb voltage relative to the reference voltage causes the i th pin to rise, which causes the current comparator to trip at a higher peak inductor current value. the average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. the ltc3872 can be used either by sensing the voltage drop across the power mosfet or by connecting the sw pin to a conventional sensing resistor in the source of the power mosfet. sensing the voltage across the power mosfet maximizes converter efficiency and minimizes the component count; the maximum rating for this pin, 60v, allows mosfet sensing in a wide output voltage range. the run/ss pin controls whether the ic is enabled or is in a low current shutdown state. with the run/ss pin below 0.85v, the chip is off and the input supply current is typically only 8a. with an external capacitor connected to the run/ss pin an optional external soft-start is enabled. a 0.7a trickle current will charge the capacitor, pulling the run/ss pin above shutdown threshold and slowly ramping run/ss to limit the v ith during start-up. because the noise on the sw pin could couple into the run/ss pin, disrupting the trickle charge current that charges the run/ss pin, a 1m resistor is recommended to pull-up the run/ss pin when external soft-start is used. when run/ss is driven by an external logic, a minimum of 2.75v logic is recommended to allow the maximum i th range. light load operation under very light load current conditions, the i th pin volt - age will be very close to the zero current level of 0.85v. as the load current decreases further, an internal offset at the current comparator input will assure that the current comparator remains tripped (even at zero load current) and the regulator will start to skip cycles, as it must, in order to maintain regulation. this behavior allows the regulator to maintain constant frequency down to ver y light loads, resulting in low output ripple as well as low audible noise and reduced rf inter ference, while providing high light load efficiency. figure 1. sw pin (internal sense pin) connection for maximum efficiency c out v sw v out v in gnd l d + ngate gnd v in sw 3872 f01 ltc3872 c out v sw r sense v out v in gnd l d + ngate gnd v in sw 3872 f02 ltc3872 figure 2. sw pin (internal sense pin) connection for sensing resistor o pera t ion ltc3872 3872fc
8 for more information www.linear.com/ltc3872 output voltage programming the output voltage is set by a resistor divider according to the following formula: v o = 1.2v ? 1+ r2 r1 ? ? ? ? the external resistor divider is connected to the output as shown in the typical application on the front page, allowing remote voltage sensing. application circuits a basic ltc3872 application circuit is shown on the front page of this datasheet. external component selection is driven by the characteristics of the load and the input supply. duty cycle considerations for a boost converter operating in a continuous conduc - tion mode (ccm), the duty cycle of the main switch is: d= v o + v d ? v in v o + v d ? ? ? ? where v d is the forward voltage of the boost diode. for converters where the input voltage is close to the output voltage, the duty cycle is low and for converters that develop a high output voltage from a low voltage input supply, the duty cycle is high. the ltc3872 has a built-in circuit that allows the extension of the maximum duty cycle while keeping the minimum switch off time unchanged. this is accomplished by reducing the clock frequency when the duty cycle is close to 80%. this function allows the user to obtain high output voltages from low input supply voltages. the shift of frequency with duty cycle is shown in the typical performance characteristics section. the peak and average input currents the control circuit in the ltc3872 is measuring the input current (either by using the r ds(on) of the power mosfet or by using a sense resistor in the mosfet source), so the output current needs to be reflected back to the input in order to dimension the power mosfet properly. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: i in(max) = i o(max) 1?d max the peak in pu t current is: i in(peak) = 1+ 2 ? ? ? ? ? i o(max) 1?d max ripple current i l and the c factor the constant c in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. for example, if 30% ripple current is chosen, then c = 0.30, and the peak current is 15% greater than the average. for a current mode boost regulator operating in ccm, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. for the ltc3872, this ramp compensation is internal. having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. if too large an inductor is used, the resulting current ramp (i l ) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). if too small an inductor is used, but the converter is still operating in ccm (continuous conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. to ensure good current mode gain and avoid subharmonic oscillation, it is recommended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. for example, if the maximum average input current is 1a, choose an i l between 0.2a and 0.4a, and a value c between 0.2 and 0.4. inductor selection given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, a pplica t ions i n f or m a t ion ltc3872 3872fc
9 for more information www.linear.com/ltc3872 the inductor value can be determined using the following equation: l = v in(min) ?i l ? f ? d max where: ?i l = ? i o(max) 1Cd max remember that boost converters are not short-circuit protected. under a shorted output condition, the induc - tor current is limited only by the input supply capability. the minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: i l(sat) 1+ 2 ? ? ? ? ? i o(max) 1?d max the saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. operating in discontinuous mode discontinuous mode operation occurs when the load cur - rent is low enough to allow the inductor current to run out during the off-time of the switch. once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1mhz to 10mhz. if the off-time is long enough, the drain voltage will settle to the input voltage. depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power mosfet to go below ground where it is clamped by the body diode. this ringing is not harmful to the ic and it has been shown not to contribute significantly to emi. any attempt to damp it with a snubber will degrade the efficiency. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a fixed inductor value, but is very dependent on the inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore, copper losses will in - crease. generally, there is a tradeoff between core losses and copper losses that needs to be balanced. ferrite designs have very low core losses and are pre - ferred at high switching frequencies, so design goals can concentrate on copper losses and preventing saturation. ferrite core material saturates hard, meaning that the inductance collapses rapidly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequently, output voltage ripple. do not allow the core to saturate! different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated field/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko and sumida. power mosfet selection the power mosfet serves two purposes in the ltc3872: it represents the main switching element in the power path and its r ds(on) represents the current sensing ele - ment for the control loop. important parameters for the power mosfet include the drain-to-source breakdown voltage (bv dss ), the threshold voltage (v gs(th) ), the on- resistance (r ds(on) ) versus gate-to-source voltage, the gate-to-source and gate-to-drain charges (q gs and q gd , respectively), the maximum drain current (i d(max) ) and the mosfets thermal resistances (r th(jc) and r th(ja) ). logic-level (4.5v v gs-rated ) threshold mosfets should be used when input voltage is high, otherwise if low input voltage operation is expected (e.g., supplying power from a lithium-ion battery or a 3.3v logic supply), then sublogic- level (2.5v v gs-rated ) threshold mosfets should be used. pay close attention to the bv dss specifications for the mosfets relative to the maximum actual switch voltage in the application. many logic-level devices are limited a pplica t ions i n f or m a t ion ltc3872 3872fc
10 for more information www.linear.com/ltc3872 to 30v or less, and the switch node can ring during the turn-off of the mosfet due to layout parasitics. check the switching waveforms of the mosfet directly across the drain and source terminals using the actual pc board layout (not just on a lab breadboard!) for excessive ringing. during the switch on-time, the control circuit limits the maximum voltage drop across the power mosfet to about 270mv, 100mv and 170mv at low duty cycle with iprg tied to v in , gnd, or left floating respectively. the peak inductor current is therefore limited to (270mv, 170mv and 100mv)/r ds(on) depending on the status of the iprg pin. the relationship between the maximum load current, duty cycle and the r ds(on) of the power mosfet is: r ds(on) v sense(max) ? 1? d max 1+ 2 ? ? ? ? ? i o(max) ? t v sense(max) is the maximum voltage drop across the power mosfet. v sense(max) is typically 270mv, 170mv and 100mv. it is reduced with increasing duty cycle as shown in figure 3. the r t term accounts for the temperature co - efficient of the r ds(on) of the mosfet, which is typically 0.4%/c. figure 4 illustrates the variation of normalized r ds(on) over temperature for a typical power mosfet. another method of choosing which power mosfet to use is to check what the maximum output current is for a given r ds(on) , since mosfet on-resistances are available in discrete values. i o(max) = v sense(max) ? 1?d max 1+ 2 ? ? ? ? ? r ds(on) ? t it is worth noting that the 1 C d max relationship between i o(max) and r ds(on) can cause boost converters with a wide input range to experience a dramatic range of maxi - mum input and output current. this should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply . voltage on the nga te pin should be within C0.3v to (v in ?+?0.3v) limits. voltage stress below C0.3v and above v in + 0.3v can damage internal mosfet driver, see func - tional diagram. this is especially important in case of driving mosfets with relatively high package inductance (dpak and bigger) or inadequate layout. a small schottky diode between nga te pin and ground can prevent nega - tive voltage spikes. t wo small schottky diodes can inhibit positive and negative voltage spikes (figure 5). junction temperature (c) ? 50 t normalized on resistance 1.0 1.5 150 3872 f04 0.5 0 0 50 100 2.0 figure 4. normalized r ds(on) vs temperature figure 5 figure 3. maximum sense threshold voltage vs duty cycle duty cycle (%) 1 0 maximum current sense voltage (mv) 50 100 150 200 250 300 20 40 60 80 3872 g03 100 iprg = high iprg = float iprg = low a pplica t ions i n f or m a t ion sw gnd v in ngate 3872 f04 ltc3872 sw gnd v in ngate ltc3872 ltc3872 3872fc
11 for more information www.linear.com/ltc3872 calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its r ds(on) ). as a result, some iterative calculation is normally required to determine a reasonably accurate value. since the controller is using the mosfet as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for v sense(max) and the r ds(on) of the mosfet listed in the manufacturers data sheet. the power dissipated by the mosfet in a boost converter is: p fet = i o(max) 1? d max ? ? ? ? 2 ? r ds(on) ? d max ? t +k ? v o 1.85 ? i o(max) 1? d max ( ) ? c rss ? f the first term in the equation above represents the i 2 r losses in the device, and the second term, the switching losses. the constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. output diode selection to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. the output diode in a boost converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage. the average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. i d(peak) =i l(peak) = 1+ 2 ? ? ? ? ? i o(max) 1?d max the power dissipated by the diode is: p d = i o(max) ? v d and the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. remember to keep the diode lead lengths short and to observe proper switch-node layout (see board layout checklist) to avoid excessive ringing and increased dis - sipation. output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct component for a given output ripple voltage. the effects of these three parameters (esr, esl and bulk c) on the output voltage ripple waveform are illustrated in figure 6e for a typical boost converter. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a per centage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging d v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging d v. this percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. a pplica t ions i n f or m a t ion ltc3872 3872fc
12 for more information www.linear.com/ltc3872 for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the fol - lowing equation: esr cout 0.01 ? v o i in(peak) where: i in(peak) = 1+ 2 ? ? ? ? ? i o(max) 1?d max for the bulk c component, which also contributes 1% to the total ripple: c out i o(max) 0.01 ? v o ? f for many designs it is possible to choose a single capacitor type that satisfies both the esr and bulk c requirements for the design. in certain demanding applications, however, the ripple voltage can be improved significantly by con - necting two or more types of capacitors in parallel. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor can be used to supply the required bulk c. once the output capacitor esr and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated pc board (see board layout section for more information on component place - ment). lab breadboards generally suffer from excessive series inductance (due to inter -component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed pc board. the output capacitor in a boost regulator experiences high rms ripple currents, as shown in figure 7. the rms output capacitor ripple current is: i rms(cout) i o(max) ? v o C v in(min) v in(min) note that the ripple current ratings from capacitor manu - facturers are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be placed in parallel to meet size or height requirements in the design. manufacturers such as nichicon, united chemicon and sanyo should be considered for high performance through- hole capacitors. the os-con semiconductor dielectric capacitor available from sanyo has the lowest product of esr and size of any aluminum electrolytic, at a somewhat higher price. in surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the esr or rms current handling requirements of the application. aluminum electrolytic and dry tantalum capacitors are v in l d sw 6a. circuit diagram 6b. inductor and input currents c out v out r l i in i l 6c. switch current i sw t on 6d. diode and output currents 6e. output voltage ripple waveform i o i d v out (ac) t off v esr ringing due to total inductance (board + cap) v cout figure 6. switching waveforms for a boost converter a pplica t ions i n f or m a t ion ltc3872 3872fc
13 for more information www.linear.com/ltc3872 both available in surface mount packages. in the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. an excellent choice is avx tps series of surface mount tantalum. also, ceramic capacitors are now available with extremely low esr, esl and high ripple current ratings. input capacitor selection the input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous (see figure 6b). the input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10f to 100f. a low esr capacitor is recommended, although it is not as critical as for the output capacitor. the rms input capacitor ripple current for a boost con - verter is: i rms(cin) = 0.3 ? v in(min) l ? f ? d max please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. be sure to specify surge-tested capacitors! efficiency considerations: how much does vds sensing help? the efficiency of a switching regulator is equal to the output power divided by the input power (100%). percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ), where l1, l2, etc. are the individual loss components as a percentage of the input power. it is often useful to analyze individua l losses to determine what is limiting the efficiency and which change would produce the most improvement. although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in ltc3872 application circuits: 1. the supply current into v in . the v in current is the sum of the dc supply current i q (given in the electrical characteristics) and the mosfet driver and control cur - rents. the dc supply current into the v in pin is typically about 250a and represents a small power loss (much less than 1%) that increases with v in . the driver current results from switching the gate capacitance of the power mosfet; this current is typically much larger than the dc current. each time the mosfet is switched on and then off, a packet of gate charge q g is transferred from v in to ground. the resulting dq/dt is a current that must be supplied to the input capacitor by an external supply. if the ic is operating in ccm: i q(tot) i q = f ? q g p ic = v in ? (i q + f ? q g ) 2. power mosfet switching and conduction losses. the technique of using the voltage drop across the power mosfet to close the current feedback loop was chosen because of the increased efficiency that results from not having a sense resistor. the losses in the power mosfet are equal to: p fet = i o(max) 1? d max ? ? ? ? 2 ? r ds(on) ? d max ? t + k ? v o 1.85 ? i o(max) 1? d max ? c rss ? f the i 2 r power savings that result from not having a discrete sense resistor can be calculated almost by inspec - tion. p r(sense) = i o(max) 1? d max ? ? ? ? 2 ? r sense ? d max to understand the magnitude of the improvement with this v ds sensing technique, consider the 3.3v input, 5v output power supply shown in the typical application on the front page. the maximum load current is 7a (10a peak) and the duty cycle is 39%. assuming a ripple current of 40%, the peak inductor current is 13.8a and the average is 11.5a. with a maximum sense voltage of about 140mv, the sense resistor value would be 10m, and the power dissipated in this resistor would be 514mw at maximum a pplica t ions i n f or m a t ion ltc3872 3872fc
14 for more information www.linear.com/ltc3872 output current. assuming an efficiency of 90%, this sense resistor power dissipation represents 1.3% of the overall input power. in other words, for this application, the use of v ds sensing would increase the efficiency by approximately 1.3%. for more details regarding the various terms in these equations, please refer to the section boost converter: power mosfet selection. 3. the losses in the inductor are simply the dc input cur - rent squared times the winding resistance. expressing this loss as a function of the output current yields: p r(winding) = i o(max) 1? d max ? ? ? ? 2 ? r w 4. losses in the boost diode. the power dissipation in the boost diode is: p diode = i o(max) ? v d the boost diode can be a major source of power loss in a boost converter. for the 3.3v input, 5v output at 7a ex - ample given above, a schottky diode with a 0.4v forward voltage would dissipate 2.8w , which represents 7% of the input power. diode losses can become significant at low output voltages where the forward voltage is a significant percentage of the output voltage. 5. other losses, including c in and c o esr dissipation and inductor core losses, generally account for less than 2% of the total additional loss. checking transient response the regulator loop response can be verified by looking at the load transient response. switching regulators generally take several cycles to respond to an instantaneous step in resistive load current. when the load step occurs, v o immediately shifts by an amount equal to (di load )(esr), and then c o begins to charge or discharge (depending on the direction of the load step) as shown in figure 7. the regulator feedback loop acts on the resulting error amp output signal to return v o to its steady-state value. during this recovery time, v o can be monitored for overshoot or ringing that would indicate a stability problem. a second, more severe transient can occur when con - necting loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c o , causing a nearly instantaneous drop in v o . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive in order to limit the inrush current di/dt to the load. boost converter design example the design example given here will be for the circuit shown on the front page. the input voltage is 3.3v, and the output is 5v at a maximum load current of 2a. 1. the duty cycle is: d = v o + v d ? v in v o + v d ? ? ? ? = 5 + 0.4 ? 3.3 5 + 0.4 = 38.9% 2. an inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: i in(peak) = 1+ 2 ? ? ? ? ? i o(max) 1? d max = 1.2 ? 2 1? 0. 39 = 3.9a the inductor ripple current is: ?i l = ? i o(max) 1Cd max = 0.4 ? 2 1C 0.39 = 1.3a figure 7. load transient response for a 3.3v input, 5v output boost converter application, 0.1a to 1a step i l 500ma/div v out 200mv/div ac-coupled 20s/div 3872 f07 a pplica t ions i n f or m a t ion ltc3872 3872fc
15 for more information www.linear.com/ltc3872 and so the inductor value is: l = v in(min) ?i l ? f ? d max = 3.3v 1.3a ? 550khz ? 0.39 = 1.8h the component chosen is a 2.2h inductor made by sumida (part number cep125-h 1romh). 3. assuming a mosfet junction temperature of 125c, the room temperature mosfet r ds(on) should be less than: r ds(on) v enss e(max) ? 1?d max 1+ 2 ? ? ? ? ? i o(max) ? t = 0.175v ? 1? 0.39 1+ 0.4 2 ? ? ? ? ? 2a ? 1.5 30m the mosfet used was the si3460, which has a maximum r ds(on) of 27m at 4.5v v gs , a bv dss of greater than 30v, and a gate charge of 13.5nc at 4.5v v gs . 4. the diode for this design must handle a maximum dc output current of 2a and be rated for a minimum reverse voltage of v out , or 5v. a 25a, 15v diode from on semi - conductor (mbrb2515l) was chosen for its high power dissipation capability. 5. the output capacitor usually consists of a lower valued, low esr ceramic. 6. the choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. for this particular design two 22f taiyo yuden ceramic capacitors (jmk325bj226mm) are required (the input and return lead lengths are kept to a few inches). as with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3872. these items are illustrated graphically in the layout diagram in figure 8. check the following in your layout: 1. the schottky diode should be closely connected between the output capacitor and the drain of the external mosfet. 2. the input decoupling capacitor (0.1f) should be con - nected closely between v in and gnd. 3. the trace from sw to the switch point should be kept short. 4. keep the switching node ngate away from sensitive small signal nodes. 5. the v fb pin should connect directly to the feedback resistors. the resistive divider r1 and r2 must be con - nected between the (+) plate of c out and signal ground. figure 8. ltc3872 layout diagram (see pc board layout checklist) iprg i th v fb gnd sw run/ss v in ngate ltc3872 3872 f08 r1 r2 r ith c in c out v out v in c ith + + d1 m1 l1 bold lines indicate high current paths a pplica t ions i n f or m a t ion ltc3872 3872fc
16 for more information www.linear.com/ltc3872 high efficiency 3.3v input, 12v output boost converter t ypical applica t ions i load 1a/div step from 500ma to 1.5a i l 5a/div v out 12v ac-coupled 100s/div 3872 f10 i th iprg gnd v fb v in sw ngate ltc3872 m1 3872 f09 run/ss 23.2k 4.7m 11.8k 1% 107k 1% c out1 : taiyo yuden tmk325b7226mm l1: coiltronics dr125-2r2 m1: vishay si4408dy 0.1f c in 10f c out1 22f 2 2.2nf 100pf c out2 120f l1 2.2h v in 3.3v v out 12v 1.5a + pds1040 ltc3872 3872fc
17 for more information www.linear.com/ltc3872 high efficiency 5v input, 12v output boost converter high efficiency 5v input, 24v output boost converter t ypical applica t ions i load 500ma/div step from 100ma to 600ma i load 5a/div v out 500s/div 3872 ta03b load (ma) 1 0 efficiency (%) 20 30 40 50 60 70 10 100 3872 ta04b 80 90 100 10 1000 i load 500ma/div step from 100ma to 600ma i load 5a/div v out 500s/div 3872 ta04c efficiency load step i th iprg gnd v fb v in sw ngate ltc3872 sbm835l 3872 ta03a run/ss 11k 4.7m 11.8k 1% 107k 1% c out1 : taiyo yuden tmk325b7226mm l1: toko d124c 892nas-3r3m m1: irf3717 c in 10f c out1 22f 2 2.2nf 100pf 1nf c out2 68f l1 3.3h m1 v in 5v v out 12v 2a + i th iprg gnd v fb v in sw ngate ltc3872 ups840 3872 ta04a run/ss 52.3k 4.7m 12.1k 1% 232k 1% c out1 : taiyo yuden umk325bj106mm-t l1: wurth we-hcf 8.2h 7443550820 m1: vishay si4174dy c in 10f c out1 10f 2 1nf 0.068f c out2 68f l1 8.2h m1 v in 5v v out 24v 1a 100pf + ltc3872 3872fc
18 for more information www.linear.com/ltc3872 high efficiency 5v input, 48v output boost converter run/ss 5v/div v out 20v/div i l 5a/div 40ms/div 3872 ta05b v out 500mv/div ac-coupled i l 2a/div i load 200ma/div 500s/div 3872 ta05c soft-start load step t ypical applica t ions load (ma) 1 60 efficiency (%) 80 100 10 100 1000 3872 ta05d 40 50 70 90 30 20 efficiency i th iprg gnd v fb v in sw ngate ltc3872 d1 m1 3872 ta05a run/ss 63.4k 1% 1m 12.1k 1% 475k 1% c in 10f c out1 2.2f 3 2.2nf 0.33f c out2 68f l1 10h v in 5v v out 48v 0.5a c out1 : nippon chemi-con kts101b225m43n d1: diodes inc. pds760 l1: sumida cdep147np-100 m1: vishay si7850dp v in + ltc3872 3872fc
19 for more information www.linear.com/ltc3872 ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 C 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.50 bsc p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltc3872 3872fc
20 for more information www.linear.com/ltc3872 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. ltc3872 3872fc
21 for more information www.linear.com/ltc3872 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number b 3/11 added i-grade and h-grade parts. changes reflected throughout the data sheet. 1 - 22 c 11/13 f osc normal operation: changed v fb from 1.2v to 1.0v changed input supply current from 10a to 8a updated mfg part number on application schematics 3 7 16, 17, 18, 22 (revision history begins at rev b) ltc3872 3872fc
22 for more information www.linear.com/ltc3872 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 2007 lt 1113 rev c ? printed in usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3872 r ela t e d p ar t s part number description comments lt ? 1619 current mode pwm controller 300khz fixed frequency, boost, sepic, flyback topology ltc1624 current mode dc/dc controller so-8; 300khz operating frequency; buck, boost, sepic design; v in up to 36v ltc1700 no r sense synchronous step-up controller up to 95% efficiency, operating as low as 0.9v input ltc1871-7 wide input range controller no r sense , 7v gate drive, current mode control ltc1872/ltc1872b sot-23 boost controller delievers up to 5a, 550khz fixed frequency, current mode lt1930 1.2mhz, sot-23 boost converter up to 34v output, 2.6v v in 16v, miniature design lt1931 inverting 1.2mhz, sot-23 converter positive-to negative dc/dc conversion, miniature design ltc3401/ltc3402 1a/2a 3mhz synchronous boost converters up to 97% efficiency, very small solution, 0.5v v in 5v ltc3704 positive-to negative dc/dc controller no r sense , current mode control, 50khz to 1mhz ltc1871/ltc1871-7 no r sense , wide input range dc/dc boost controller no r sense , current mode control, 2.5v v in 36v ltc3703/ltc3703-5 100v synchronous controller step-up or step down, 600khz, ssop-16, ssop-28 ltc3803/ltc3803-5 200khz flyback dc/dc controller optimized for driving 6v mosfets thinsot 3.3v input, 5v/2a output boost converter typical a pplica t ion i th iprg gnd v fb v in sw ngate ltc3872 d1 m1 3872 ta02 run/ss 17.4k v in 11k 1% 34.8k 1% c in 10f c out 100f 2 1.8nf 47pf l1 1h v in 3.3v v out 5v 2a d1: diodes inc. b320 l1: toko fdv0630-1r0 m1: vishay si3460ddv 1 m 1nf ltc3872 3872fc

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